sig02 Project Status (05/17/2022 - 08:27:10)
Project File:	sig02.xise	Parser Errors:	No Errors
Module Name:	sig02	Implementation State:	Programming File Generated
Target Device:	xc3s500e-5pq208	Errors:	No Errors
Product Version:	ISE 12.2	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	203	9,312	2%
Number of 4 input LUTs	486	9,312	5%
Number of occupied Slices	257	4,656	5%
Number of Slices containing only related logic	257	257	100%
Number of Slices containing unrelated logic	0	257	0%
Total Number of 4 input LUTs	504	9,312	5%
Number used as logic	486
Number used as a route-thru	18
Number of bonded IOBs	12	158	7%
IOB Flip Flops	4
Number of BUFGMUXs	6	24	25%
Average Fanout of Non-Clock Nets	2.46

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue May 17 08:25:21 2022	0	0	0
Translation Report	Current	Tue May 17 08:26:02 2022	0	0	0
Map Report	Current	Tue May 17 08:26:05 2022	0	0	2 Infos (2 new)
Place and Route Report	Current	Tue May 17 08:26:24 2022	0	0	3 Infos (3 new)
Power Report
Post-PAR Static Timing Report	Current	Tue May 17 08:26:27 2022	0	0	5 Infos (5 new)
Bitgen Report	Current	Tue May 17 08:27:09 2022	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Out of Date	Tue May 17 08:20:07 2022
WebTalk Report	Current	Tue May 17 08:27:09 2022
WebTalk Log File	Current	Tue May 17 08:27:10 2022

Date Generated: 05/17/2022 - 08:27:10