### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.

Software Version and Target Device
Product Version: | ISE:12.2 (WebPack) - M.63c | Target Family: | Spartan3E
OS Platform: | NT64 | Target Device: | xc3s500e
Project ID (random number) | a096e44a06b34057b3bf0bf81ac2b440.1652E9E6BB654406AE4F86467A151603.1 | Target Package: | pq208
Registration ID | 0_0_0 | Target Speed: | -5
Date Generated | 2022-05-17T08:27:09 | Tool Flow | ISE

User Environment
OS Name | Microsoft | OS Release | Service Pack 1 (build 7601)
CPU Name | Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz | CPU Speed | 3192 MHz

Device Usage Statistics
Macro Statistics | Miscellaneous Statistics | Net Statistics | Site Usage
Comparators=6 32-bit comparator less=6 Counters=6 32-bit down counter=6 Registers=15 Flip-Flops=15 | MiscellaneousStatistics AGG_BONDED_IO=12 AGG_IO=12 AGG_SLICE=257 NUM_4_INPUT_LUT=504 NUM_BONDED_IBUF=2 NUM_BONDED_IOB=10 NUM_BUFGMUX=6 NUM_CYMUX=300 NUM_IOB_FF=4 NUM_LUT_RT=18 NUM_SLICEL=257 NUM_SLICE_FF=203 NUM_XOR=198 | NetStatistics NumNets_Active=559 NumNets_Gnd=1 NumNets_Vcc=1 NumNodesOfType_Active_CLKPIN=111 NumNodesOfType_Active_CNTRLPIN=111 NumNodesOfType_Active_DOUBLE=613 NumNodesOfType_Active_DUMMY=973 NumNodesOfType_Active_DUMMYESC=2 NumNodesOfType_Active_GLOBAL=74 NumNodesOfType_Active_HFULLHEX=10 NumNodesOfType_Active_HLONG=2 NumNodesOfType_Active_HUNIHEX=34 NumNodesOfType_Active_INPUT=1117 NumNodesOfType_Active_IOBOUTPUT=2 NumNodesOfType_Active_OMUX=554 NumNodesOfType_Active_OUTPUT=551 NumNodesOfType_Active_PREBXBY=139 NumNodesOfType_Active_VFULLHEX=44 NumNodesOfType_Active_VLONG=16 NumNodesOfType_Active_VUNIHEX=22 NumNodesOfType_Vcc_CNTRLPIN=6 NumNodesOfType_Vcc_INPUT=17 NumNodesOfType_Vcc_PREBXBY=17 NumNodesOfType_Vcc_VCCOUT=19 SiteStatistics IBUF-DIFFSI=1 IOB-DIFFM=5 IOB-DIFFS=5 SLICEL-SLICEM=94 | SiteSummary BUFGMUX=6 BUFGMUX_GCLKMUX=6 BUFGMUX_GCLK_BUFFER=6 IBUF=2 IBUF_INBUF=2 IBUF_PAD=2 IOB=10 IOB_OFF1=4 IOB_OUTBUF=10 IOB_PAD=10 SLICEL=257 SLICEL_C1VDD=111 SLICEL_C2VDD=124 SLICEL_CYMUXF=156 SLICEL_CYMUXG=144 SLICEL_F=252 SLICEL_FFX=96 SLICEL_FFY=107 SLICEL_G=252 SLICEL_GNDF=45 SLICEL_GNDG=20 SLICEL_XORF=96 SLICEL_XORG=102

Configuration Data
BUFGMUX S=[S_INV:6] [S:0] BUFGMUX_GCLKMUX DISABLE_ATTR=[LOW:6] S=[S_INV:6] [S:0] IBUF_PAD IOATTRBOX=[LVCMOS25:2] IOB O1=[O1_INV:4] [O1:6] OTCLK1=[OTCLK1_INV:0] [OTCLK1:4] SR=[SR:0] [SR_INV:4] IOB_OFF1 CK=[CK:4] [CK_INV:0] D=[D:0] [D_INV:4] LATCH_OR_FF=[FF:4] OFF1_INIT_ATTR=[INIT1:4] OFF1_SR_ATTR=[SRHIGH:4] OFFATTRBOX=[ASYNC:4] SR=[SR:0] [SR_INV:4] | IOB_OUTBUF IN=[IN_INV:0] [IN:10] IOB_PAD DRIVEATTRBOX=[12:10] IOATTRBOX=[LVCMOS25:10] SLEW=[SLOW:10] SLICEL BX=[BX_INV:0] [BX:18] BY=[BY:5] [BY_INV:0] CIN=[CIN_INV:0] [CIN:138] CLK=[CLK:107] [CLK_INV:0] SR=[SR:0] [SR_INV:107] SLICEL_CYMUXF 0=[0:156] [0_INV:0] 1=[1_INV:0] [1:156] | SLICEL_CYMUXG 0=[0:144] [0_INV:0] SLICEL_FFX CK=[CK:96] [CK_INV:0] D=[D:96] [D_INV:0] FFX_INIT_ATTR=[INIT0:88] [INIT1:8] FFX_SR_ATTR=[SRLOW:88] [SRHIGH:8] LATCH_OR_FF=[FF:96] SR=[SR:0] [SR_INV:96] SYNC_ATTR=[ASYNC:96] SLICEL_FFY CK=[CK:107] [CK_INV:0] D=[D:107] [D_INV:0] FFY_INIT_ATTR=[INIT0:98] [INIT1:9] FFY_SR_ATTR=[SRLOW:98] [SRHIGH:9] LATCH_OR_FF=[FF:107] SR=[SR:0] [SR_INV:107] SYNC_ATTR=[ASYNC:107] | SLICEL_XORF 1=[1_INV:0] [1:96]

Pin Data
BUFGMUX I0=6 O=6 S=6 BUFGMUX_GCLKMUX I0=6 OUT=6 S=6 BUFGMUX_GCLK_BUFFER IN=6 OUT=6 IBUF I=2 PAD=2 IBUF_INBUF IN=2 OUT=2 IBUF_PAD PAD=2 IOB O1=10 OTCLK1=4 PAD=10 SR=4 IOB_OFF1 CK=4 D=4 Q=4 SR=4 | IOB_OUTBUF IN=10 OUT=10 IOB_PAD PAD=10 SLICEL BX=18 BY=5 CIN=138 CLK=107 COUT=144 F1=252 F2=138 F3=42 F4=41 G1=246 G2=145 G3=48 G4=46 SR=107 X=96 XQ=96 Y=96 YQ=107 | SLICEL_C1VDD 1=111 SLICEL_C2VDD 1=124 SLICEL_CYMUXF 0=156 1=156 OUT=156 S0=156 SLICEL_CYMUXG 0=144 1=144 OUT=144 S0=144 SLICEL_F A1=252 A2=138 A3=42 A4=41 D=252 SLICEL_FFX CK=96 D=96 Q=96 SR=96 | SLICEL_FFY CK=107 D=107 Q=107 SR=107 SLICEL_G A1=246 A2=145 A3=48 A4=46 D=252 SLICEL_GNDF 0=45 SLICEL_GNDG 0=20 SLICEL_XORF 0=96 1=96 O=96 SLICEL_XORG 0=102 1=102 O=102

Tool Usage
Command Line History xst -intstyle ise -ifn <ise_file> ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf bitgen -intstyle ise -f <fname>.ut <fname>.ncd fuse

Software Quality
Run Statistics
_impact | 12 | 11 | 0 | 0 | 0 | 0 | 0
bitgen | 11 | 11 | 0 | 0 | 0 | 0 | 0
map | 24 | 20 | 0 | 0 | 0 | 0 | 0
ngdbuild | 23 | 23 | 0 | 0 | 0 | 0 | 0
par | 20 | 20 | 0 | 0 | 0 | 0 | 0
trce | 20 | 20 | 0 | 0 | 0 | 0 | 0
xst | 32 | 32 | 0 | 0 | 0 | 0 | 0

Project Statistics
PROP_Enable_Message_Filtering=false | PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced | PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false | PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/sig02 | PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed | PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false | PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2022-05-17T08:16:23 | PROP_intWbtProjectID=1652E9E6BB654406AE4F86467A151603
PROP_intWbtProjectIteration=1 | PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No | PROP_selectedSimRootSourceNode_behav=work.sig02
PROP_AutoTop=true | PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s500e | PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=pq208 | PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 | PROP_PreferredLanguage=VHDL
FILE_UCF=1 | FILE_VHDL=1

Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=5 | NGDBUILD_NUM_BUFGP=1 | NGDBUILD_NUM_FDC=186 | NGDBUILD_NUM_FDP=21
NGDBUILD_NUM_GND=1 | NGDBUILD_NUM_IBUF=1 | NGDBUILD_NUM_INV=208 | NGDBUILD_NUM_LUT1=18
NGDBUILD_NUM_LUT2=193 | NGDBUILD_NUM_LUT3=3 | NGDBUILD_NUM_LUT4=87 | NGDBUILD_NUM_MUXCY=300
NGDBUILD_NUM_OBUF=10 | NGDBUILD_NUM_VCC=1 | NGDBUILD_NUM_XORCY=192
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=6 | NGDBUILD_NUM_FDC=186 | NGDBUILD_NUM_FDP=21 | NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=1 | NGDBUILD_NUM_IBUFG=1 | NGDBUILD_NUM_INV=208 | NGDBUILD_NUM_LUT1=18
NGDBUILD_NUM_LUT2=193 | NGDBUILD_NUM_LUT3=3 | NGDBUILD_NUM_LUT4=87 | NGDBUILD_NUM_MUXCY=300
NGDBUILD_NUM_OBUF=10 | NGDBUILD_NUM_VCC=1 | NGDBUILD_NUM_XORCY=192

ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=139 ms, 18132 KB
Total Signals=29
Total Nets=29
Total Blocks=4
Total Processes=13
Total Simulation Time=1 s
Simulation Resource Usage=48.5787 sec, 472895 KB
Simulation Mode=gui
Hardware CoSim=0